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lt c2508-32 1 250832f for more information www.linear.com/ltc2508-32 typical application features description 32-bit over-sampling adc with configurable digital filter the lt c ? 2508-32 is a low noise, low power, high-perfor - mance 32- bit adc with an integrated configurable digital filter . operating from a single 2.5v supply, the ltc2508-32 features a fully differential input range up to v ref , with v ref ranging from 2.5v to 5.1v . the ltc2508 -32 supports a wide common mode range from 0v to v ref simplifying analog signal conditioning requirements. the ltc2508 -32 simultaneously provides two output codes: (1) a 32- bit digitally filtered high precision low noise code, and (2) a 22- bit no latency composite code. the configurable digital filter reduces measurement noise by lowpass filtering and down-sampling the stream of data from the sar adc core, giving the 32- bit filtered output code. the 22- bit composite code consists of a 14- bit code representing the differential voltage and an 8- bit code representing the common mode voltage. the 22- bit composite code is available each conversion cycle, with no cycle of latency. the digital filter can be easily configured for 4 different down-sampling factors by pin strapping. the configura - tions provide a dynamic range of 131db at 3.9ksps and 145db at 61sps. the digital lowpass filter relaxes the re- quirements for analog anti-aliasing. multiple ltc2508-32 devices can be easily synchronized using the sync pin. applications n 0.5ppm inl (typ) n 145db dynamic range (typ) at 61sps n 131db dynamic range (typ) at 4ksps n guaranteed 32-bits no missing codes n configurable digital filter with synchronization n relaxed anti-aliasing filter requirements n dual output 32-bit sar adc n 32-bit digitally filtered low noise output n 14-bit differential + 8-bit common mode 1msps no latency output n wide input common-mode range n guaranteed operation to 85c n 1.8v to 5v spi-compatible serial i/o n low power: 24mw at 1msps n 24-lead 7mm 4mm dfn package n seismology n energy exploration n automated test equipment (ate) n high-accuracy instrumentation l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9054727, 9231611, 9331709 and patents pending. 2.5v in + in C differential differential inputs in + / in C with wide input common mode range arbitrary unipolar bipolar ref gnd ltc2508-32 rdla drl rdlb sdoa sckasckb sdob busy mclk v dd v ref 0v 0v v ref v ref 0v 0v v ref ov dd 10f 0.1f 1.8v to 5.1v 2.5v to 5.1v sampleclock 250832 ta01 47f(x7r, 1210 size) in + , in C 32-bit sar adc core 32-bit14-bit pin selectable low-pass wideband digital filter integral nonlinearity vs input voltage input voltage (v) 250832 ta01a C5 C2.5 0 2.5 5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.0 inl error (ppm) downloaded from: http:///
lt c2508-32 2 250832f for more information www.linear.com/ltc2508-32 pin configuration absolute maximum ratings supply voltage (v dd ) ............................................... 2.8v supply voltage (ov dd ) ................................................ 6v reference input (ref) ................................................. 6v analog input voltage (note 3) in + , in C ......................... (gnd C 0.3v ) to (ref + 0.3v ) digital input voltage (note 3) .......................... (gnd C 0.3v ) to (ov dd + 0.3v ) digital output voltage (note 3) .......................... (gnd C 0.3v ) to (ov dd + 0.3v ) power dissipation .............................................. 500mw operating temperature range lt c2508 c-32 ........................................... 0c to 70 c lt c2508 i-32 ........................................ C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) top view 25 gnd dkd package 24-lead (7mm 4mm) plastic dfn rdla 1 rdlb 2 v dd 3 gnd 4 in + 5 in C 6 gnd 7 ref 8 ref 9 ref 10 sel0 11 sel1 12 24 gnd 23 gnd 22 ov dd 21 busy20 sdob 19 sckb 18 scka 17 sdoa 16 gnd 15 drl 14 sync 13 mclk t jmax = 125c, ja = 40c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l 0 v ref v v in C absolute input range (in C ) (note 5) l 0 v ref v v in + C v in C input differential voltage range v in = v in + C v in C l Cv ref v ref v v cm common-mode input range l 0 v ref v i in analog input leakage current 10 na c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio filtered output v in + = v in C = 4.5v p-p , 200hz sine 128 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) lead free finish tape and reel part marking* package description temperature range ltc2508cdkd-32#pbf ltc2508cdkd-32#trpbf 250832 24-lead (7mm 4mm) plastic dfn 0c to 70c ltc2508idkd-32#pbf ltc2508idkd-32#trpbf 250832 24-lead (7mm 4mm) plastic dfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/ltc2508-32#orderinfo downloaded from: http:///
lt c2508-32 3 250832f for more information www.linear.com/ltc2508-32 dynamic accuracy for filtered output (sdoa) converter characteristics for filtered output (sdoa) symbol parameter conditions min typ max units dr dynamic range v ref = 5v, df = 256 in + = in C = v cm , v ref = 5v, df = 1024 in + = in C = v cm , v ref = 5v, df = 4096 in + = in C = v cm , v ref = 5v, df = 16384 l 125 131 136 141 145 db db db db thd total harmonic distortion f in = 200hz, v ref = 2.5v, df = 256 f in = 200hz, v ref = 5v, df = 256 l C118 C118 C108 db db sfdr spurious free dynamic range f in = 200hz, v ref = 2.5v, df = 256 f in = 200hz, v ref = 5v, df = 256 l 108 118 118 db db C3db input bandwidth 34 mhz aperture delay 500 ps aperture jitter 4 ps rms transient response full-scale step 125 ns symbol parameter conditions min typ max units resolution l 32 bits no missing codes l 32 bits df down-sampling factor l 256 16384 transition noise df = 256 (note 6) df = 1024 df = 4096 df = 16384 0.095 0.055 0.03 0.02 ppm ppm ppm ppm inl integral linearity error (note 7) l C3.5 0.5 3.5 ppm zse zero-scale error (note 9) l C13 0 13 ppm zero-scale error drift 14 ppb/c fse full-scale error (note 9) l C100 10 100 ppm full-scale error drift 0.05 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = ?20dbfs. (notes 4, 10) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
lt c2508-32 4 250832f for more information www.linear.com/ltc2508-32 converter characteristics for no latency output (sdob)reference input digital inputs and digital outputs symbol parameter conditions min typ max units resolution: differential common mode l l 14 8 bits bits no missing codes: differential common mode l l 14 8 bits bits transition noise differential common mode (note 6) 1 1 lsb rms lsb rms inl integral linearity error differential common mode (note 7) 0.1 0.1 lsb lsb dnl differential linearity error differential common mode 0.1 0.1 lsb lsb zse zero scale error differential common mode 1 1 lsb lsb fse zero scale error differential common mode 1 1 lsb lsb symbol parameter conditions min typ max units v ref reference voltage (note 5) l 2.5 5.1 v i ref reference input current (note 11) l 0.7 1 ma symbol parameter conditions min typ max units v ih high level input voltage l 0.8?ov dd v v il low level input voltage l 0.2?ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 4, 9) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
lt c2508-32 5 250832f for more information www.linear.com/ltc2508-32 power requirements adc timing characteristics symbol parameter conditions min typ max units v dd supply voltage l 2.375 2.5 2.625 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i pd supply current supply current power down mode 1msps sample rate 1msps sample rate (c l = 20pf) conversion done (i vdd + i ovdd + i ref ) l l 9.5 1 6 13 350 ma ma a p d power dissipation power down mode 1msps sample rate (i vdd ) conversion done (i vdd + i ovdd + i ref ) 24 15 32.5 875 mw w symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1 msps f dra output data rate at sdoa l 3.9 ksps f drb output data rate at sdob l 1 msps t conv conversion time l 578 652 ns t acq acquisition time t acq = t cyc C t conv C t busylh (note 8) l 335 ns t cyc time between conversions l 1000 ns t mclkh mclk high time l 20 ns t mclkl minimum low time for mclk (note 12) l 20 ns t busylh mclk to busy delay c l = 20pf l 13 ns t drllh mclk to drl delay c l = 20pf l 18 ns t quiet scka, sckb quiet time from mclk (note 8) l 10 ns t scka scka period (notes 12, 13) l 10 ns t sckah scka high time l 4 ns t sckal scka low time l 4 ns t dsdoa sdoa data valid delay from scka c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 8.5 8.5 9.5 ns ns ns t hsdoa sdoa data remains valid delay from scka c l = 20pf (note 8) l 1 ns t dsdoadrll sdoa data valid delay from drl c l = 20pf (note 8) l 5 ns t enaa bus enable time after rdla (note 12) l 16 ns t disa bus relinquish time after rdla (note 12) l 13 ns t sckb sckb period (notes 12, 13) l 10 ns t sckbh sckb high time l 4 ns t sckbl sckb low time l 4 ns t dsdob sdob data valid delay from sckb c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 8.5 8.5 9.5 ns ns ns t hsdob sdob data remains valid delay from sckb c l = 20pf (note 8) l 1 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
lt c2508-32 6 250832f for more information www.linear.com/ltc2508-32 adc timing characteristics symbol parameter conditions min typ max units t dsdobbusyl sdob data valid delay from busy c l = 20pf (note 8) l 5 ns t enb bus enable time after rdlb (note 12) l 16 ns t disb bus relinquish time after rdlb (note 12) l 13 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above ref or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above ref or ov dd without latch-up.note 4: v dd = 2.5v, ov dd = 2.5v, ref = 5v, v cm = 2.5v, f smpl = 1mhz, df = 256.note 5: recommended operating conditions. note 6: transition noise is defined as the noise level of the adc with in + and in C shorted. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: guaranteed by design, not subject to test. note 9: bipolar zero-scale error is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 0000 0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 10: all specifications in db are referred to a full-scale 5v input with a 5v reference voltage.note 11: f smpl = 1mhz, i ref varies proportionally with sample rate. note 12: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 13: t scka , t sckb of 10ns maximum allows a shift clock frequency up to 100mhz for rising edge capture. 0.8?ov dd 0.2?ov dd 50% 50% 250832 f01 0.2?ov dd 0.8?ov dd 0.2?ov dd 0.8?ov dd t delay t width t delay figure 1. voltage levels for specifications downloaded from: http:///
lt c2508-32 7 250832f for more information www.linear.com/ltc2508-32 typical performance characteristics integral nonlinearity vs input voltage integral nonlinearity vs input voltage dc histogram, df = 256 dc histogram, df = 1024 dc histogram, df = 4096 dc histogram, df = 16384 128k point fft f smpl = 1msps, f in = 200hz, df = 256 128k point fft f smpl = 1msps, f in = 50hz, df = 1024 t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 1msps, df = 256, filtered output, unless otherwise noted. input voltage (v) 250832 g01 C5 C2.5 0 2.5 5 C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.0 inl error (ppm) = 0.095ppm output code (ppm) C0.4 C0.2 0 0.2 0.4 0 200 400 600 800 1000 counts 250832 g04 = 0.055ppm output code (ppm) C0.4 C0.2 0 0.2 0.4 0 200 400 600 800 1000 counts 250832 g05 = 0.03ppm output code (ppm) C0.4 C0.2 0 0.2 0.4 0 200 400 600 800 1000 counts 250832 g06 = 0.02ppm output code (ppm) C0.4 C0.2 0 0.2 0.4 0 200 400 600 800 1000 counts 250832 g07 250832 g08 dr = 131db frequency (khz) 0 0.5 1 1.5 2 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) 250832 g09 dr = 136db frequency (hz) 0 122 244 366 488 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) arbitrary drive in + /in C swept 0 to 5v input voltage (v) C5 C2.5 0 2.5 5 C3.5 C1.8 0 1.8 3.5 inl error (ppm) 250832 g03 32k point fft f smpl = 1msps, f in = 10hz, df = 4096 250832 g09 dr = 141db frequency (hz) 0 30 61 91 122 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) downloaded from: http:///
lt c2508-32 8 250832f for more information www.linear.com/ltc2508-32 8k point fft f smpl = 1msps, f in = 10hz, df = 16384 dynamic range, transition noise vs df frequency response, df = 256, 1024, 4096, 16384 snr, sinad vs input level, f in = 200hz dynamic range vs reference voltage, f in = 200hz, a in = ?20dbfs thd, harmonics vs reference voltage, f in = 200hz, a in = ?1dbfs dynamic range vs temperature, f in = 100hz, a in = ?20dbfs typical performance characteristics t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 1msps, df = 256, filtered output, unless otherwise noted. shutdown current vs temperature thd, harmonics vs temperature, f in = 200hz, a in = ?1dbfs 250832 g10 dr = 145db frequency (hz) 0 7 15 23 31 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) 250832 g11 down sampling factor (df) 256 1024 4096 16384 125 130 135 140 145 150 0 0.02 0.04 0.06 0.08 0.10 dynamic range (db) transition noise (ppm) 250832 g14 reference voltage (v) 2.5 3 3.5 4 4.5 5 122 124 126 128 130 132 134 dr (db) 250832 g15 thd 3rd 2nd reference (v) 2.5 3 3.5 4 4.5 5 C130 C125 C120 C115 C110 harmonics, thd (dbfs) 250832 g16 temperature ( o c) C40 C15 10 35 60 85 120 125 130 135 140 dr (db) 250832 g18 thd 3rd 2nd temperature ( o c) C40 C15 10 35 60 85 C140 C130 C120 C110 harmonics, thd (dbfs) 250832 g12 0 f smpl /1024 f smpl /512 3f smpl /1024 f smpl /256 C150 C100 C50 0 df=16384 df=4096 df=1024 df=256 250832 g13 snr sinad input level (db) C40 C30 C20 C10 0 110 115 120 125 130 135 140 snr,sinad (dbfs) temperature (c) C40 C15 10 35 60 85 0 10 20 30 40 powerCdown current (a) 250832 g17 downloaded from: http:///
lt c2508-32 9 250832f for more information www.linear.com/ltc2508-32 typical performance characteristics inl vs temperature full-scale error vs temperature offset error vs temperature supply current vs temperature common mode rejection vs input frequency reference current vs reference voltage t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 1msps, df = 256, filtered output, unless otherwise noted. max inl min inl temperature (c) C40 C15 10 35 60 85 C4 C3 C2 C1 0 1 2 3 4 inl error (ppm) 250832 g19 250832 g20 Cfs +fs temperature ( o c) C40 C15 10 35 60 85 C10 C5 0 5 10 fullCscale error (ppm) temperature (c) C40 C15 10 35 60 85 C5 C4 C3 C2 C1 0 1 2 3 4 5 zeroCscale error (ppm) 250832 g21 i vdd i ref temperature (c) C40 C15 10 35 60 85 0 1 2 3 4 5 6 7 8 9 10 power supply current (ma) i ovdd 250832 g22 frequency (mhz) 0.0001 0.001 0.01 0.1 1 2 75 100 125 150 175 200 cmrr (db) 250832 g23 reference voltage (v) 2.5 3 3.5 4 4.5 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 reference current (a) 250832 g24 downloaded from: http:///
lt c2508-32 10 250832f for more information www.linear.com/ltc2508-32 typical performance characteristics no latency differential output inl vs input voltage no latency differential output dnl vs input voltage no latency common mode output 128k point fft t a = 25c, v dd = 2.5v, ov dd = 2.5v, v cm = 2.5v, ref = 5v, f smpl = 1msps, df = 256, no latency output, unless otherwise noted. input voltage (v) C5 C2.5 0 2.5 5 C0.5 C0.4 C0.3 C0.1 0 0.1 0.3 0.4 0.5 inl error (lsb) 250832 g27 input voltage (v) C5 C2.5 0 2.5 5 C0.5 C0.4 C0.3 C0.1 0 0.1 0.3 0.4 0.5 dnl error (lsb) 250832 g28 snr = 48db frequency (khz) 0 125 250 375 500 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) 250832 g29 no latency differential output 128k point fft snr = 86db frequency (khz) 0 125 250 375 500 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) 250832 g26 downloaded from: http:///
lt c2508-32 11 250832f for more information www.linear.com/ltc2508-32 pin functions rdla (pin 1) : read low input a (filtered output). when rdla is low, the serial data output a (sdoa) pin is enabled. when rdla is high, sdoa pin is in a high-impedance state. logic levels are determined by ov dd . rdlb (pin 2) : read low input b (no latency output). when rdlb is low, the serial data output b (sdob) pin is enabled. when rdlb is high, sdob pin is in a high- impedance state. logic levels are determined by ov dd . v dd (pin 3) : 2.5v power supply. the range of v dd is 2.375v to 2.625v . bypass v dd to gnd with a 10f ce - ramic capacitor. gnd (pins 4, 7, 16, 23, 24): ground. in + (pin 5): positive analog input. in ? (pin 6): negative analog input. ref (pins 8, 9, 10) : reference input. the range of ref is 2.5v to 5.1v . this pin is referred to the gnd pin and should be decoupled closely to the pin with a 47f ceramic capacitor (x7r, 1210 size, 10v rating).sel0 , se l1 (pins 11, 12) : down-sampling factor select input 0, down-sampling factor select input 1. selects the down-sampling factor for the digital filter. down-sampling factors of 256, 1024, 4096 and 16384 are selected for [sel0 se l1] combinations of 00, 01, 10 and 11 respec - tively. logic levels are determined by ov dd . mclk (pin 13) : master clock input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . sync (pin 14) : synchronization input. a pulse on this input is used to synchronize the phase of the digital filter. logic levels are determined by ov dd . drl (pin 15) : data ready low output. a falling edge on this pin indicates that a new filtered output code is available in the output register of sdoa. logic levels are determined by ov dd . sdoa (pin 17) : serial data output a (filtered output). the filtered output code appears on this pin (msb first) on each rising edge of scka. the output data is in 2 s complement format. logic levels are determined by ov dd . scka (pin 18) : serial data clock input a (filtered output). when sdoa is enabled, the filtered output code is shifted out (msb first) on the rising edges of this clock. logic levels are determined by ov dd . sckb (pin 19) : serial data clock input b (no latency output). when sdob is enabled, the no latency output code is shifted out (msb first) on the rising edges of this clock. logic levels are determined by ov dd . sdob (pin 20) : serial data output b (no latency output). the 22- bit no latency composite output code appears on this pin (msb first) on each rising edge of sckb. the output data is in 2 s complement format. logic levels are determined by ov dd . busy (pin 21) : busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . ov dd (pin 22) : i/o interface digital power. the range of ov dd is 1.71v to 5.25v . this supply is nominally set to the same supply as the host interface ( 1.8v, 2.5v, 3.3v, or 5v ). bypass ov dd to gnd (pin 23) close to the pin with a 0.1f capacitor. gnd (exposed pad pin 25) : ground. exposed pad must be soldered directly to the ground plane. downloaded from: http:///
lt c2508-32 12 250832f for more information www.linear.com/ltc2508-32 functional block diagram in + ref = 5v v dd = 2.5v ov dd = 1.8v to 5v in C 32-bit sar adc sckasdoa rdla ltc2508-32 spi port +C mclk busy drl sync sel0 sel1 250832 fbd gnd control logic sckbsdob rdlb digital filter 14 32 downloaded from: http:///
lt c2508-32 13 250832f for more information www.linear.com/ltc2508-32 timing diagram da31 da29 da27 da25 da23 da21 da19 da17 da15 da13 da11 da9 da7 da5 da3 da1 wa7 wa5 wa3 wa1 da30 da28 da26 da24 da22 da20 da18 da16 da14 da12 da10 da8 da6 da4 da2 da0 wa6 wa4 wa2 wa0 db13 mclk drl rdla = rdlb = 0 convert scka sdoa sckb sdob busy db11 db9 db7 db5 db3 db1 cb7 cb5 cb3 250832 td db12 db10 db8 db6 db4 db2 db0 cb6 cb4 cb2 cb1 cb0 convert power down and acquire conversion timing using the serial interface downloaded from: http:///
lt c2508-32 14 250832f for more information www.linear.com/ltc2508-32 figure 2. ltc2508-32 transfer function applications information overview the ltc2508 -32 is a low noise, low power, high-perfor - mance 32- bit adc with an integrated configurable digital filter . operating from a single 2.5v supply, the ltc2508-32 features a fully differential input range up to v ref , with v ref ranging from 2.5v to 5.1v . the ltc2508 -32 supports a wide common mode range from 0v to v ref simplifying analog signal conditioning requirements. the ltc2508 -32 simultaneously provides two output codes: (1) a 32- bit digitally filtered high precision low noise code, and (2) a 22- bit no latency composite code. the configurable digital filter reduces measurement noise by lowpass filtering and down-sampling the stream of data from the sar adc core, giving the 32- bit filtered output code. the 22- bit composite code consists of a 14- bit code representing the differential voltage and an 8- bit code representing the common mode voltage. the 22- bit composite code is available each conversion cycle, with no cycle of latency. the digital filter can be easily configured for 4 different down-sampling factors by pin strapping. the configura - tions provide a dynamic range of 131db at 3.9ksps and 145db at 61sps. the digital lowpass filter relaxes the re- quirements for analog anti-aliasing. multiple ltc2508-32 devices can be easily synchronized using the sync pin.conver ter opera tion the ltc2508 -32 operates in two phases. during the ac - quisition phase, a 32- bit charge redistribution capacitor d/a converter (cdac) is connected to the in + and in C pins to sample the analog input voltages. a rising edge on the mclk pin initiates a conversion. during the conversion phase, the 32- bit cdac is sequenced through a succes - sive approximation algorithm, effectively comparing the sampled inputs with binary-weighted fractions of the refer - ence voltage (e.g. v ref /2, v ref /4 v ref /4294967296). at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then passes the 32- bit digital output code to the digital filter for further processing. a 14- bit code representing the differential voltage and an 8- bit code representing the common mode voltage are combined to form a 22- bit composite code. the 22- bit composite code is available each conversion cycle, without any cycle of latency. transfer function the ltc2508 -32 digitizes the full-scale differential voltage of 2 v ref into 2 32 levels, resulting in an lsb size of 2.3nv with a 5v reference. the ideal transfer function is shown in figure 2. the output data is in 2 s complement format. analog input the ltc2508 -32 samples the voltage difference (in + C in C ) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode rejec - tion ratio (cmrr) of the adc. wide common mode input range coupled with high cmrr allows the in + /in C analog inputs to swing with an arbitrary relationship to each other, provided each pin remains between gnd and v ref . this unique feature of the ltc2508 -32 enables it to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudo-differential unipo - lar, pseudo-differential true bipolar, and fully differential, thereby simplifying signal chain design. in the acquisition phase, each input sees approximately 45pf (c in ) from the sampling circuit in series with 40 (r on ) from the on-resistance of the sampling switch. input voltage (v) 0v output code (twos complement) C1 lsb 250832 f02 011...111 011...110000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 C 1lsb Cfsr/2 fsr = +fs C Cfs1lsb = fsr/4294967296 downloaded from: http:///
lt c2508-32 15 250832f for more information www.linear.com/ltc2508-32 applications information the inputs draw a current spike while charging the c in capacitors during acquisition. during conversion, the analog inputs draw only a small leakage current. input drive circuits a low impedance source can directly drive the high imped - ance inputs of the ltc2508 -32 without gain error. a high impedance sour ce should be buffered to minimize settling time during acquisition and to optimize adc linearity . for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2508 -32. the amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs. noise and distortion the noise and distortion of an input buffer amplifier and other supporting circuitry must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier with a low bandwidth filter to minimize noise. the simple one-pole rc lowpass filter (l pf1 ) shown in figure 4 is sufficient for many applications.a coupling filter network (l pf2 ) should be used between the buffer and adc input to minimize disturbances reflected into the buffer from sampling transients. long rc time constants at the analog inputs will slow down the settling ref 250832 f03 ref bias voltage in + in C r on 40 c in 45pf r on 40 c in 45pf figure 3. the equivalent circuit for the differential analog input of the ltc2508-32 figure 4. filtering input signal of the analog inputs. therefore, l pf2 typically requires wider bandwidth than l pf1 . this filter also helps minimize the noise contribution from the buffer. a buffer amplifier with a low noise density must be selected to minimize degradation of snr. 10 3300pf 6600pf 10 500 lpf2 lpf1 bw = 1.2mhz bw = 48khz single-ended- to-differential driver single-ended- input signal ltc2508-32 in + in C 250832 f04 6800pf 6800pf high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input currents an important consideration when coupling an amplifier to the ltc2508 -32 is in dealing with current spikes drawn by the adc inputs at the start of each acquisition phase. the adc inputs may be modeled as a switched capacitor load of the drive circuit. a drive circuit may rely partially on attenuating switched-capacitor current spikes with small filter capacitors c filt placed directly at the adc inputs, and partially on the driver amplifier having suffi - cient bandwidth to recover from the residual disturbance. amplifiers optimized for dc performance may not have sufficient bandwidth to fully recover at the adc s maximum conversion rate, which can produce nonlinearity and other errors. coupling filter circuits may be classified in three broad categories: downloaded from: http:///
lt c2508-32 16 250832f for more information www.linear.com/ltc2508-32 applications information figure 5. equivalent circuit for the differential analog input of the ltc2508-32 at 1msps figure 6. common mode and differential input leakage current over temperature fully settled C this case is characterized by filter time constants and an overall settling time that is consider- ably shorter than the sample period. when acquisition begins, the coupling filter is disturbed. for a typical first order rc filter, the disturbance will look like an initial step with an exponential decay. the amplifier will have its own response to the disturbance, which may include ringing. if the input settles completely (to within the accuracy of the ltc2508 -32), the disturbance will not contribute any error. partially settled C in this case, the beginning of acquisi - tion causes a disturbance of the coupling filter, which then begins to settle out towards the nominal input voltage. however, acquisition ends (and the conversion begins) before the input settles to its final value. this generally produces a gain error , but as long as the settling is linear, no distortion is produced. the coupling filter s response is affected by the amplifier s output impedance and other parameters. a linear settling response to fast switched- capacitor current spikes can not always be assumed for precision, low bandwidth amplifiers. the coupling filter serves to attenuate the current spikes high-frequency energy before it reaches the amplifier. fully averaged C if the coupling filter capacitors (c filt ) at the adc inputs are much larger than the adc s sample capacitors ( 45pf ), then the sampling glitch is greatly at - tenuated. the driving amplifier effectively only sees the average sampling current, which is quite small. at 1msps, the equivalent input resistance is approximately 22k (as shown in figure 5), a benign resistive load for most precision amplifiers. however, resistive voltage division will occur between the coupling filter s dc resistance and the adc s equivalent (switched-capacitor) input resistance, thus producing a gain error. the input leakage currents of the ltc2508 -32 should also be considered when designing the input drive circuit, because source impedances will convert input leakage currents to an added input voltage error. the input leakage currents, both common mode and differential, are typically extremely small over the entire operating temperature range. figure 6 shows the input leakage currents over temperature for a typical part. c filt >>45pf ltc2508-32 bias voltage in + 22k (r eq ) 22k (r eq ) in C c filt >>45pf r eq = f smpl ? 45pf 1 let r s1 and r s2 be the source impedances of the dif - ferential input drive circuit shown in figure 7, and let i l1 and i l2 be the leakage currents flowing out of the adc s analog inputs. the differential voltage error, v e , due to the leakage currents can be expressed as: v e = r s1 + r s2 2 i l1 ?i l2 ( ) + r s1 ?r s2 ( ) i l1 + i l2 2 the common mode input leakage current, (i l1 + i l2 )/2, is typically extremely small (figure 6) over the entire operat - ing temperature range and common mode input voltage range. thus, any reasonable mismatch (below 5%) of the sour ce impedances r s1 and r s2 will cause only a negligible error. the differential leakage current is also typically very small, and its nonlinear component is even smaller. only the nonlinear component will impact the adcs linearity. common v in = v ref differential temperature (c) 250832 f06 C40 C15 10 35 60 85 C5 C2 1 4 7 10 input leakage (na) downloaded from: http:///
lt c2508-32 17 250832f for more information www.linear.com/ltc2508-32 applications information for optimal performance, it is recommended that the source impedances, r s1 and r s2 , be between 5 and 50 and with 1% tolerance. for source impedances in this range, the voltage and temperature coefficients of r s1 and r s2 are usually not critical. the guaranteed ac and dc specifications are tested with 5 source imped - ances, and the specifications will gradually degrade with increased sour ce impedances due to incomplete settling. dc accuracy the ltc2508 -32 has excellent inl specifications. this makes the ltc2508 -32 ideal for applications which re - quire high dc accuracy, including parameters such as offset and offset drift. t o maintain high accuracy over the entire dc signal chain, amplifiers have to be selected ver y carefully. a large-signal open-loop gain of at least 126db may be required to ensure 1ppm linearity for amplifiers configured for a gain of negative 1. however, less gain is sufficient if the amplifier s gain characteristic is known to r s1 r s2 i l1 i l2 250832 f07 in + v e in C +C ltc2508-32 figure 7. source impedances of a driver and input leakage currents of the ltc2508-32 figure 8. buffering two analog input signals 2.5v in + in C ref gnd ltc2508-32 v dd ov dd 10f 0.1f 1.8v to 5.1v 2.5v to 5.1v 250832 f08 47f(x7r, 1210 size) v in + C + + C 4.7f 0.047f0.047f 4.99k4.99k 10 ltc2057 ltc2057 10 4.7f v in C be (mostly) linear. an amplifier s offset versus signal level must be considered for amplifiers configured as unity gain buffers. for example, 1ppm linearity may require that the offset is known to vary less than 5v for a 5v swing. however, greater offset variations may be acceptable if the relationship is known to be (mostly) linear. unity-gain buffer amplifiers typically require substantial headroom to the power supply rails for best performance. inverting ampli - fier circuits configured to minimize swing at the amplifier input terminals may per form better with less headroom than unity-gain buffer amplifiers. the linearity and thermal properties of an inverting amplifier s feedback network should be considered carefully to ensure dc accuracy. buffering input signals the wide common mode input range and high cmrr of the ltc2508 -32 allow analog inputs in + and in C pins to swing with an arbitrary relationship to each other, provided that each pin remains between v ref and gnd. this unique feature of the ltc2508 -32 enables it to accept a wide variety of signal swings, simplifying signal chain design. buffering dc accurate input signals figure 8 shows a typical application where two analog input voltages are buffered using the ltc2057 . the ltc2057 is a high precision zero drift amplifier which complements the low offset and offset drift of the ltc2508 -32. the ltc2057 is shown in a non-inverting amplifier configura - downloaded from: http:///
lt c2508-32 18 250832f for more information www.linear.com/ltc2508-32 applications information figure 10a. buffering ac inputs tion. the ltc2508 -32 has a guaranteed maximum offset error of 130v (typical drift 0.014ppm/ c), and a guar - anteed maximum full-scale error of 150ppm (typical drift 0.05ppm / c). low drift is important to maintain accuracy over a wide temperature range in a calibrated system. buffering dc accurate single-ended input signals while the circuit shown in figure 8 is capable of buffering single-ended input signals, the circuit shown in figure 9 is preferable when the single-ended signal reference level is inherently low impedance and doesn t require buffering. this circuit eliminates one driver and one lowpass filter, reducing part count, power dissipation, and snr degrada - tion due to driver noise. the ltc2057 has excellent dc characteristics, but limited output current drive, leading to a degradation in thd as the input frequency increases. limit the input frequency to 10hz to maintain full data sheet specified thd. figure 9. buffering single-ended signals 2.5v in + in C ref gnd ltc2508-32 v dd ov dd 10f 4.7f 0.047f 4.99k 10 v in + 0.1f 250832 f09 1.8v to 5.1v 2.5v to 5.1v 47f(x7r, 1210 size) C + ltc2057 buffering ac input signals many driver circuits presented in this data sheet emphasize performance for low bandwidth input signals, and the amplifiers are chosen accordingly. while the ltc2057 is characterized by excellent dc specifications, its output current drive is limited. this limits the range of input fre - quencies that the ltc2057 can drive to the full data sheet specifications of the ltc2508 -32. the C3db bandwidth of the filtered output of the ltc2508 -32, while operating with a df of 256, is equal to 480hz . therefore, an alternative driver solution is required while driving input signals with bandwidth greater than 10hz. the ltc6363 is a low power, low noise, fully differential op amp, and can be used to drive input signals with bandwidth greater than 10hz . the ltc6363 may be configured to convert a single-ended input signal to a differential output signal or may be driven differentially. figure 10a shows the ltc6363 being used to buffer a 10v differential input signal. in this case, the amplifier is configured as a unity gain buffer using the lt5400-4 precision resistors. as shown in the fft of figure 10b , the ltc6363 drives the ltc2508 -32 to near full data sheet performance. lt5400-4 1k 0.1f 0.1f C3v 0.1f 8v v cm 6800pf 6800pf 6800pf 250832 f10a in + v in C v in + in C 30.130.1 1k1k 1k C + ltc6363 downloaded from: http:///
lt c2508-32 19 250832f for more information www.linear.com/ltc2508-32 applications information figure 10b. 128k point fft with f in = 200hz for circuit shown in figure 10a figure 11. mclk waveform showing burst sampling adc referencean external reference defines the input range of the ltc2508 -32. a low noise, low temperature drift reference is critical to achieving the full data sheet performance of the adc. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power and high accuracy, the ltc6655 -5 is particularly well suited for use with the ltc2508 -32. the ltc6655 -5 offers 0.025% (max) initial accuracy and 2ppm/ c (max) temperature coefficient for high precision applications. when choosing a bypass capacitor for the ltc6655 -5, the capacitor s voltage rating, temperature rating, and pack - age size should be carefully considered. physically larger capacitors with higher voltage and temperature ratings tend to provide a larger effective capacitance, better filtering the noise of the ltc6655 -5, and consequently facilitating a higher snr. therefore, we recommend bypassing the ltc6655 -5 with a 47f ceramic capacitor (x7r, 1210 size, 10v rating) close to the ref pin.the ref pin of the ltc2508 -32 draws charge (q conv ) from the 47f bypass capacitor during each conversion cycle. mclk 250832 f11 idle period idle period the reference replenishes this charge with an average current, i ref = q conv /t cyc . the current drawn from the ref pin, i ref , depends on the sampling rate and output code. if the ltc2508 -32 continuously samples a signal at a constant rate, the ltc6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5ppm. when idling, the ref pin on the ltc2508-32 draws only a small leakage current ( < 1a ). in applications where a burst of samples is taken after idling for long periods as shown in figure 11, i ref quickly goes from approximately 0a to a maximum of 1ma at 1msps . this step in average current drawn causes a transient response in the refer - ence that must be considered, since any deviation in the reference output voltage will affect the accuracy of the output code. in applications where the transient response of the reference is important, the fast settling ltc6655-5 reference is also recommended.reference noise the dynamic range of the adc will increase approximately 6db for every 4 increase in the down-sampling factor (df). the snr should also improve as a function of df in the same manner. for large input signals near full-scale, however, any reference noise will limit the improvement of the snr as df increases, because any noise on the ref pin will modulate around the fundamental frequency of the input signal. therefore, it is critical to use a low-noise refer - ence, especially if the input signal amplitude approaches full-scale. for small input signals, the dynamic range will improve as described earlier in this section. dynamic performance fast fourier t ransform (ff t) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, 250832 f10b dr = 130db frequency (khz) 0 0.5 1 1.5 2 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) downloaded from: http:///
lt c2508-32 20 250832f for more information www.linear.com/ltc2508-32 applications information figure 12. 128k point fft plot of ltc2508-32 with df = 256, f in = 200hz and f smpl = 1mhz the adc s spectral content can be examined for frequen - cies outside the fundamental. the ltc2508 -32 provides guaranteed tested limits for both ac distortion and noise measurements. dynamic range the dynamic range is the ratio of the rms value of a full scale input t o the total rms noise measured with the inputs shorted to v ref /2. the dynamic range of the ltc2508-32 with df = 256 is 131db which improves with increase in the down-sampling factor. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 12 shows that the ltc2508 -32 achieves a typical sinad of 120db at a 1mhz sampling rate with a 200hz input, and df = 256. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + ! + vn 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. power considerations the ltc2508 -32 has two power supply pins : the 2.5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2508 -32 to communicate with any digital logic operating between 1.8v and 5v , including 2.5v and 3.3v systems.power supply sequencing the ltc2508 -32 does not have any specific power sup - ply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2508- 32 has a power-on-reset (por) circuit that will reset the ltc2508 -32 at initial power-up or whenever the power supply voltage drops below 1v . once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 200s after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control mclk timing a rising edge on mclk will power up the ltc2508-32 and start a conversion. once a conversion has been started, further transitions on mclk are ignored until the conversion is complete. for best results, the falling edge signal-to-noise ratio (snr)the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 12 shows that the ltc2508 -32 achieves an snr of 125db when sampling a 200hz input at a 1mhz sampling rate with df = 256. 250832 f12 snr = 128db frequency (khz) 0 0.5 1 1.5 2 C200 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 amplitude (dbfs) downloaded from: http:///
lt c2508-32 21 250832f for more information www.linear.com/ltc2508-32 applications information of mclk should occur within 40ns from the start of the conversion, or after the conversion has been completed. for optimum performance, mclk should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. once the conversion has completed, the ltc2508 -32 powers down and begins acquiring the input signal for the next conversion.internal conversion clock the ltc2508 -32 has internal timing circuity that is trimmed to achieve a maximum conversion time of 652ns . with a maximum sample rate of 1msps , a minimum acquisition time of 335ns is guaranteed without any external adjust - ments. auto power down the ltc2508 -32 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of mclk. during power-down, data from the last conversion can be clocked out. to minimize power dissipation during power- down, disable sdoa, sdob and turn off scka, sckb. the auto power-down feature will reduce the power dissipa - tion of the ltc2508 -32 as the sampling rate is reduced. since power is consumed only during a conversion, the ltc2508 -32 remains powered down for a larger fraction of the conversion cycle (t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 13. decimation filters many adc applications use digital filtering techniques to reduce noise. an fpga or dsp is typically needed to implement a digital filter. the ltc2508 -32 features an in - tegrated decimation filter that provides 4 selectable digital filtering functions without any external hardware, thus simplifying the application solution. figure 14 shows the ltc2508 -32 digitally filtered output signal path, wherein the output d adc (n) of the 32- bit sar adc core is passed on to the integrated decimation filter. digital filter 32-bit sar adc core down sampler integrated decimation filter 250832 f14 v in d out (k) d adc (n) d 1 (n) figure 14. ltc2508-32 digitally filtered output signal path figure 15. frequency spectrum of sar adc core output figure 13. power supply current of the ltc2508-32 vs sampling rate digital filteringthe input to the ltc2508 -32 is sampled at a rate f smpl , and digital words d adc (n) are transmitted to the digital filter at that rate. noise from the 32- bit sar adc core is distributed uniformly in frequency from dc to f smpl . figure?15 shows the frequency spectrum of d adc (n) at the output of the sar adc core. in this example, the bandwidth of interest f b is a small fraction of f smpl /2. d adc 250832 f15 f b f smpl /2 i vdd i ovdd i ref sampling rate (msps) 250832 f13 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 12 supply current (ma) downloaded from: http:///
lt c2508-32 22 250832f for more information www.linear.com/ltc2508-32 applications information figure 16. frequency spectrum of digital filter core output figure 17. time domain view of aliasing d 1 digital filter cutoff frequency 250832 f16 f b f smpl /2 the digital filter integrated in the ltc2508 -32 suppresses out-of-band noise power, thereby lowering overall noise and increasing the dynamic range (dr). the lower the filter bandwidth, the lower the noise, and the higher the dr. figure 16 shows the corresponding frequency spectrum of d 1 (n) at the output of the digital filter, where noise beyond the cutoff frequency is suppressed by the digital filter. down-sampling the output data rate of the digital filter is reduced by a down-sampler without causing spectral interference in the bandwidth of interest. the down-sampler reduces the data rate by passing ev - ery df th sample to the output, while discarding all other samples. the sampling frequency f o at the output of the down sampler is the ratio of f smpl and df, i.e., f o = f smpl /df. the ltc2508 -32 enables the user to select df according to a desired bandwidth of interest. the 4 available con - figurations can be selected by pin strapping pins se l0 and se l1 . table 1 summarizes the different decimation filter configurations and properties. table 1. properties of filters in ltc2508-32 sel1:sel0 down sampling factor (df) ?3db bandwidth when f smpl = 1mhz output data rate (odr) when f smpl = 1mhz dynamic range 00 256 480hz 3906sps 131db 01 1024 120hz 796sps 136db 10 4096 30hz 244sps 141db 11 16384 7.5hz 61sps 145db aliasing the maximum bandwidth that a signal being sampled can have and be accurately represented by its samples is the nyquist bandwidth. the nyquist bandwidth ranges from dc to half the sampling frequency (a.k.a. the nyquist frequency). an input signal whose bandwidth exceeds the nyquist frequency, when sampled, will experience distortion due to an effect called aliasing. when aliasing, frequency components greater than the nyquist frequency undergo a frequency shift and appear within the nyquist bandwidth. figure 17 illustrates aliasing in the time domain. the solid line shows a sinusoidal input signal of a frequency greater than the nyquist frequency (f o /2). the circles show the signal sampled at f o . note that the sampled signal is identical to that of sampling another sinusoidal input signal of a lower frequency shown with the dashed line. to avoid aliasing, it is necessary to band-limit an input signal to the nyquist bandwidth before sampling it. a filter that suppresses spectral components outside the nyquist bandwidth is called an anti-aliasing filter (aaf). anti-aliasing filtersfigure 18 shows a typical signal chain including a lowpass aaf and an adc sampling at a rate of f o . the aaf rejects input signal components exceeding f o /2, thus avoiding aliasing. if the bandwidth of interest is close to f o /2, then input signal 250832 f17 sampled signal (aliased) downloaded from: http:///
lt c2508-32 23 250832f for more information www.linear.com/ltc2508-32 applications information the aaf must have a very steep roll-off. the complexity of the analog aaf increases with the steepness of the roll-off, and it may be prohibitive if a very steep filter is required. alternatively, a simple low-order analog filter in combination with a digital filter can be used to create a mixed-mode equivalent aaf with a very steep roll-off. a mixed-mode filter implementation is shown in figure 19 where an analog filter with a gradual roll-off is followed by the ltc2508 -32 sampling at a rate of f smpl = df ? f o . the ltc2508 -32 has an integrated digital filter at the output of the adc core. the equivalent aaf, h eq (f), is the product of the frequency responses of the analog filter h 1 (f) and digital filter h 2 (f), as shown in figure 20. the digital filter provides a steep roll-off, allowing the analog filter to have a relatively gradual roll-off. the digital filter in the ltc2508 -32 operates at the adc sampling rate f smpl and suppresses signals at frequencies exceeding f o /2. the frequency response of the digital filter h 2 (f) repeats at multiples of f smpl , resulting in unwanted pass-bands at each multiple of f smpl . the analog filter should be designed to provide adequate suppression of the unwanted pass-bands, such that h eq (f) has only one pass-band corresponding to the frequency range of interest. larger df settings correspond to less bandwidth of the digital filter, allowing for the analog filter to have a more gradual roll-off. a simple first- or second-order analog filter will provide adequate suppression for most systems. analog filter ltc2508 digital filter df down-sampler image v in f smpl f smpl = df f o f smpl f smpl C f 0 /2 h 1 h 2 d 1 (n) d out (k) at f 0 (sps) f 0 /2 f 0 /2 f smpl C f 0 /2 250832 f19 adc core analog filter digital filter v in f smpl f smpl f smpl C f 0 /2 f smpl C f 0 /2 h 1 h 2 f 0 /2 f 0 /2 250832 f20 equivalent aaf to adc f smpl h eq f 0 /2 figure 19. mixed-mode filter signal chain figure 20. mixed-mode anti-aliasing filter (aaf) figure 18. adc signal chain with aaf anti-aliasing filter adc v in f 0 d out (k) f 0 f 0 /2 250832 f18 downloaded from: http:///
lt c2508-32 24 250832f for more information www.linear.com/ltc2508-32 applications information figure 21. frequency response of digital filter with df = 256 figure 22. step response of ltc2508-32 frequency response of digital filtersfigure 21 shows the frequency response of the digital filter when the ltc2508 -32 is configured to operate with df?=?256 and sampling at f smpl . for each configuration of the ltc2508 -32, the digital filter is a lowpass finite impulse response (fir) filter with linear phase response. the bandwidth is inversely proportional to the selected df value. each configuration provides a minimum of 80db attenuation for frequencies in the range of f o /2 and f smpl C f o /2. the filter coefficients 10 C2 C1 0 1 group delay output sample number 2 3 4 5 6 7 8 9 10 11 analog step input signal digital filter output d 1 (n) ltc2508 output samples d out (k) 250832 f22 and detailed version of the frequency response of the 4 digital filter configurations are available at www.linear.com/ docs/52896. table?2 lists the length and group delay of each digital filters impulse response. table 2. length of digital filter down-sampling factor (df) length of digital filter impulse response group delay (f smpl = 1msps) 256 2,304 1.2ms 1,024 9,216 4.6ms 4,096 36,864 18.4ms 16,384 147,456 73.7ms settling time and group delay the length of each digital filter s impulse response deter - mines its settling time. linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). group delay of the digital filter is defined to be the delay to the center of the impulse response. ltc2508 -32 is optimized for low latency, and it pro - vides fast settling. figure 22 shows the output settling behavior after a step change on the analog inputs of the ltc2508 -32. the x axis is given in units of output sample number. the step response is representative for all values of df. full settling is achieved in 10 output samples. 250832 f21 0 f s m p l /1024 f s m p l /512 3f s m p l /1024 f s m p l /256 C150 C100 C50 0 downloaded from: http:///
lt c2508-32 25 250832f for more information www.linear.com/ltc2508-32 applications information digital interface the ltc2508 -32 features two digital serial interfaces. serial interface a is used to read the filtered output data. serial interface b is used to read the no latency output data. both interfaces support a flexible ov dd supply, al - lowing the ltc2508 -32 to communicate with any digital logic operating between 1.8v and 5v , including 2.5v and 3.3v systems. filtered output datafigure 23 shows a typical operation for reading the filtered output data. the i/o register contains filtered output codes d out (k) provided by the decimation filter. d out (k) is up - dated once in every df number of conversion cycles. a timing signal drl indicates when d out (k) is updated. drl goes high at the beginning of every df th conversion, and it goes low when the conversion completes. the 32-bits of d out (k) can be read out before the beginning of the next a/d conversion. scka 250832 f23 1 32 1 32 1 32 d out (0) d out (1) d out (2) d out (3) filtered output register (register updated once every df conversions) df number of conversions df number of conversions df number of conversions conversion number mclk 1 2 df 2df+2 df+1 df+2 2df 2df+1 3df drl 250832 f24 32 scka conversion number filtered output register mclk 0 1 2 df 3 31 32 33 df+1 drl scka df number of conversions 1 2 3 32 1 d out (0) d out (1) (register updated once for every df conversions) 1 scka 1 scka 1 scka 1 scka 0 scka 1 scka/cnv figure 23. typical filtered output data operation timing figure 24. reading out filtered output data with distributed read downloaded from: http:///
lt c2508-32 26 250832f for more information www.linear.com/ltc2508-32 applications information figure 25. synchronization using a single sync pulse distributed readltc2508 -32 enables the user to read out the contents of the i/o register over multiple conversions. figure 24 shows a case where one bit of d out (k) is read for each of 32 consecutive a/d conversions, enabling the use of a much slower serial clock (scka). transitions on the digital interface should be avoided during a/d conversion operations (when busy is high). synchronization the output of the digital filter d 1 (n) is updated every conversion, whereas the down-sampler output d out (k) is updated only once every df number of conversions. synchronization is the process of selecting when the output d out (k) is updated. this is done by applying a pulse on the sync pin of the ltc2508 -32. the i/o register for d out (k) is updated at each multiple of df number of conversions after a sync pulse is provided, as shown in figure 25. a timing signal drl indicates when d out (k) is updated. the sync function allows multiple ltc2508 devices, operated from the same master clock that use common sync signal, to be synchronized with each other. this allows each ltc2508 device to update its output register at the same time. note that all devices being synchronized must operate with the same df. 250832 f25 conversion number filtered output register mclk 1 2 df 2df+2 df+1 df+2 2df 2df+1 3df drl sync df number of conversions df number of conversions df number of conversions d out (0) d out (1) d out (2) d out (3) downloaded from: http:///
lt c2508-32 27 250832f for more information www.linear.com/ltc2508-32 figure 26. synchronization using a periodic sync pulse 250832 f26 conversion number filtered output register mclk drl 1 2 df 2df+2 df+1 df+2 2df 2df+1 3df 3df+1 sync synchronization window d out (0) d out (1) d out (2) d out (3) synchronization window synchronization window applications information periodic synchronization sync pulses that reinforce an existing synchronization do not interfere with normal operation. figure 26 shows a case where a sync pulse is applied for each df number of conversions to continually reinfor ce a synchroniza - tion. figure 26 indicates synchronization windows when a sync pulse may be applied to reinforce the synchronized operation. self-correcting synchronizationfigure 27 shows a case where an unexpected glitch on mclk causes an extra a/d conversion to occur. this extra conversion alters the update instants for d out (k). the applied periodic sync pulse reestablishes the desired synchronization and self corrects within one conversion cycle. note that the digital filter is reset when the synchro - nization is changed (reestablished). 250832 f27 user conversion number user provided mclk corrupted mclk drl w/o periodic sync drl with periodic sync df number of conversions periodic sync unwanted glitch expected drl 1 2 dfC1 2df df df+1 2dfC1 2df+1 2df+2 synchronization window df number of conversions expected drl corrected drl figure 27. recovering synchronization from unexpected glitch downloaded from: http:///
lt c2508-32 28 250832f for more information www.linear.com/ltc2508-32 applications information no latency output datafigure 28 shows a typical operation for reading the no latency output data. the no latency i/o register holds a 22- bit composite code r(n) from the most recent sample taken of inputs in + and in C at the rising edge of mclk. the first 14 bits of r(n) represent the input voltage dif - ference (in + C in C ), msb first. the last 8 bits represent the common-mode input voltage (in + + in C )/2, msb first. figure 29. frequency response of digital filter with df = 16384 50hz and 60hz rejectionfigure 29 shows the frequency response of the digital filter in the ltc2508 -32 configured to operate with df = 16384, and f smpl = 1msps . as shown, at least 100db simultane - ous suppression of 50hz and 60hz is obtained. note that the frequency axis shown in figure 29 scales with f smpl . configuration word an 8- bit configuration word, wa [7:0] , is appended to the 32- bit output code on sdoa to produce a total output word of 40 bits as shown in figure 30. the configura - tion word designates which downsampling factor (df) the digital filter is configured to operate with. clocking out the configuration word is optional. t able 3 lists the configuration words for each df value. da31 da29 da27 da25 da23 da21 da19 da17 da15 da13 da11 da9 da7 da5 da3 da1 wa7 wa5 wa3 wa1 da30 da28 da26 da24 da22 da20 da18 da16 da14 da12 da10 da8 da6 da4 da2 da0 wa6 wa4 wa2 wa0 mclk drl convert scka sdoa 250832 f30 figure 30. using ltc2508-3 to read filtered output table 3. configuration word for different df values df wa [7:0] 256 10000101 1,024 10100101 4,096 11000101 16,384 11100101 250832 f28 conversion number mclk busy sckb no-latency output register 0 1 2 3 4 5 6 1 1 22 r(0) r(1) r(2) r(3) r(4) r(5) r(6) 22 1 22 1 22 1 22 1 22 1 22 figure 28. typical nyquist output data operation timing 250832 f29 0 10 20 30 frequency (hz) 40 50 60 C120 C100 C80 C60 magnitude (db) C40 C20 0 df=16384 downloaded from: http:///
lt c2508-32 29 250832f for more information www.linear.com/ltc2508-32 filtered output data, single device, df = 256figure 31 shows an ltc2508 -32 configured to operate with df = 256. with rdla grounded, sdoa is enabled and msb ( da31 ) of the output result is available t dsdoadrll after the falling edge of drl. applications information figure 31. using a single ltc2508-32 with df = 256 to read filtered output mclk drl rdla master clk mclk rdla = gnd convert power-down and acquire t mclkh t cyc t mclkl drl scka sdoa da31 da30 da29 da1 da0 wa7 250832 f31 irqclk data in digital host sel0sel1 sdoa scka ltc2508-32 convert t conv t drllh t dsdoadrll t scka 1 2 3 30 31 32 t sckah t sckal t hsdoa t dsdoa t quiet downloaded from: http:///
lt c2508-32 30 250832f for more information www.linear.com/ltc2508-32 applications information filtered output data, multiple devices, df = 256figure 32 shows two ltc2508 -32 devices configured to operate with df = 256, while sharing mclk, sync, scka and sdoa. by sharing mclk, sync, scka and sdoa, the number of required signals to operate multiple adcs in parallel is reduced. since sdoa is shared, the rdla input mclk drl rdla syncirq master clk 250832 f32 rdla x rdla y clk data in digital host sel0 syncsel1 sdoa scka ltc2508-32 y mclk rdlasel0 syncsel1 sdoa scka ltc2508-32 x drl scka 1 2 3 30 31 32 33 34 35 62 63 64 sdoa sync rdla x rdla y t conv t scka t quiet t sckah t sckal t dsdoa t hsdoa t drllh t ena t disa hi-z hi-z da31x da30x da29x da31y da30y da29y da1y da0y wa7y hi-z da1x da0x wa7x mclk convert power-down and acquire t mclkl convert figure 32. reading filtered output with multiple devices sharing mclk, scka and sdoa of each adc must be used to allow only one ltc2508-32 to drive sdoa at a time in order to avoid bus conflicts. as shown in figure 32, the rdla inputs idle high and are individually brought low to read data out of each device between conversions. when rdla is brought low, the msb of the selected device is output on sdoa. downloaded from: http:///
lt c2508-32 31 250832f for more information www.linear.com/ltc2508-32 applications information figure 33. using a single ltc2508-32 to read no latency output no latency output data, single devicefigure 33 shows a single ltc2508 -32 configured to read the no latency data out. with rdlb grounded, sdob is enabled and msb ( db13 ) of the output result is available t dsdobbusyl after the falling edge of busy. 250832 f33 busy t conv t busylh t acq t acq = t cyc C t conv C t busylh sckb t sckb 1 2 3 20 21 22 t sckbh t sckbl t quiet sdob db13 db12 db11 cb1 cb0 t dsdobbusyl t hsdob t dsdob mclk rdlb = gnd convert power-down and acquire t mclkh t cyc t mclkl convert mclk busy rdlb master clkirq clk data in digital host sdob sckb ltc2508-32 downloaded from: http:///
lt c2508-32 32 250832f for more information www.linear.com/ltc2508-32 no latency output data, multiple devicesfigure 34 shows multiple ltc2508 -32 devices configured to read no latency data out, while sharing mclk, sckb and sdob. by sharing mclk, sckb and sdob, the number of required signals to operate multiple adcs in parallel is reduced. since sdob is shared, the rdlb input of each applications information adc must be used to allow only one ltc2508 -32 to drive sdob at a time in order to avoid bus conflicts. as shown in figure 34, the rdlb inputs idle high and are individu - ally brought low to read data out of each device between conversions. when rdlb is brought low, the msb of the selected device is output on sdob. mclk busy rdlb rdlb x irq master clk 250832 f34 rdlb y clk data in digital host sdob sckb ltc2508-32 y mclk rdlb sdob sckb ltc2508-32 x busy sckb 1 2 3 20 21 22 23 24 25 42 43 44 sdob rdlb x rdlb y t conv t sckb t quiet t sckbh t sckbl t dsdob t hsdob t busylh t enb t disb hi-z hi-z hi-z db13x db12x db11x db13y db12y db11y cb1y cb0y cb1x cb0x mclk convert power-down and acquire t mclkl convert figure 34. reading no latency output with multiple devices sharing mclk, sckb and sdob downloaded from: http:///
lt c2508-32 33 250832f for more information www.linear.com/ltc2508-32 applications information figure 35. reading filtered output and no latency output by sharing sck, and sdo shared sdo bus at a time in order to avoid bus conflicts. as shown in figure 35, the rdla and rdlb inputs idle high and are individually brought low to read data from each serial output when data is available. when rdla is brought low, the msb of the filtered output data from sdoa is output on the shared sdo bus. when rdlb is brought low, the msb of the no latency data output from sdob is output on the shared sdo bus. mclk drl rdlbsel0 sel1 rdla rdlairq master clk 250832 f35 rdlbclk data in digital host sdob sdoa sckb scka ltc2508-32 drl scka/ sckb sdoa/ sdob 1 2 3 30 31 32 33 34 35 52 53 54 busy rdlardlb t conv t scka t sckb t quiet t sckah t sckal t dsdoa t hsdoa t drllh t conv t busylh t sckbh t sckbl t hsdob t ena t disa t enb hi-z hi-z hi-z da31 da30 da29 db13 db12 db11 cb1 cb0 da1 da0 wa7 t dsdob mclk convert power-down and acquire t mclkl convert filtered output data, no latency data, single devicefigure 35 shows a single ltc2508 -32 configured to read both filtered and no latency output data, while sharing sdoa with sdob and scka with sckb. sharing signals reduces the total number of required signals to read both the filtered and no latency data from the adc. since sdoa and sdob are shared, the rdla and rdlb inputs of the adc must be used to allow only one output to drive the downloaded from: http:///
lt c2508-32 34 250832f for more information www.linear.com/ltc2508-32 board layout to obtain the best performance from the ltc2508 -32, a four-layer printed circuit board (pcb) is recommended. layout for the pcb should ensure the digital and analog signal lines are separated as much as possible. in particu - lar, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. supply bypass capacitors should be placed as close as possible to the supply pins. low impedance common re - turns for these bypass capacitors are essential to the low noise operation of the adc. a single solid ground plane is recommended for this purpose. when possible, screen the analog input traces using ground. reference design for a detailed look at the reference design for this con - verter, including schematics and pcb layout, please refer to dc2222 , the evaluation kit for the ltc2508-32. dc2222 is designed to achieve the full data sheet performance of the ltc2508 -32. customer board layout should copy dc2222 grounding, and placement of bypass capacitor as closely as possible. downloaded from: http:///
lt c2508-32 35 250832f for more information www.linear.com/ltc2508-32 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/product/ltc2508-32#packaging for the most recent package drawings. note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) bottom viewexposed pad r = 0.115 typ 0.25 0.05 1 12 13 24 5.50 ref 6.43 0.10 2.64 0.10 4.00 0.10 0.75 0.05 0.00 C 0.05 0.200 ref 7.00 0.10 (dkd24) dfn 0210 rev ? 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer 6.43 0.05 2.64 0.05 0.70 0.05 0.50 bsc 5.50 ref 3.10 0.05 4.50 0.05 0.40 0.10 0.25 0.05 package outline r = 0.05 typ dkd package 24-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1864 rev ?) downloaded from: http:///
lt c2508-32 36 250832f for more information www.linear.com/ltc2508-32 ? linear technology corporation 2016 lt 0716 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2508-32 related parts typical application part number description comments ltc2380-24 24-bit, 1.5/2msps, 0.5ppm inl serial, low power adc 2.5v supply, 5v fully differential input, 100db snr, msop-16 and 4mm 3mm dfn-16 packages ltc2368-24 24-bit, 1msps, 0.5ppm inl serial, low power adc with unipolar input range 2.5v supply, 0v to 5v fully unipolar input, 98db snr, msop-16 and 4mm 3mm dfn-16 package ltc2378-20/ltc2377-20/ ltc2376-20 20-bit, 1msps/500ksps/250ksps, 0.5ppm inl serial, low power adc 2.5v supply, 5v fully differential input, 104db snr, msop-16 and 4mm 3mm dfn-16 package dacs ltc2757 18-bit, single parallel i out softspan? dac 1lsb inl/dnl, software-selectable ranges, 7mm 7mm lqfp-48 package ltc2641 16-bit/14-bit/12-bit single serial v out dac 1lsb inl/dnl, msop-8 package, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references ltc6655 precision low drift low noise buffered reference 5v/4.906v/3.3v/3v/2.5v/2.048v/1.25v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/4.906v/3.3v/3v/2.5v/2.048v/1.25v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers ltc2057 low noise zero-drift operational amplifier 4v offset v oltage, 0.015v/c offset voltage drift ltc6363 low power, fully differential output amplifier/driver single 2.8v to 11v supply, 1.9ma supply current, msop-8 and 2mm 3mm dfn-8 package ltc6362 low power , fully differential input/ output amplifier/driver single 2.8v to 5.25v supply, 1ma supply current, msop-8 and 3mm 3mm dfn-8 package 2.5v 5v C + 0.1f 0.1f 8v C3v vcm 6800pf 6800pf 6800pf 250832 ta02 ltc6363 v in + 30.130.1 2k 2k 1k 1k 0.1f C10v 0v 10v ltc2508-32 in + in C gnd v dd ref buffering and converting a 10v true bipolar input signal to a fully differential adc input downloaded from: http:///

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